Espressif Systems /ESP32-P4 /SDHOST /CLK_EDGE_SEL

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Interpret as CLK_EDGE_SEL

Description

SDIO control register.

Fields

CCLKIN_EDGE_DRV_SEL	It’s used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270.
CCLKIN_EDGE_SAM_SEL	It’s used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270.
CCLKIN_EDGE_SLF_SEL	It’s used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270.
CCLLKIN_EDGE_H	The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.
CCLLKIN_EDGE_L	The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.
CCLLKIN_EDGE_N	The clock division of cclk_in.
ESDIO_MODE	Enable esdio mode.
ESD_MODE	Enable esd mode.
CCLK_EN	Sdio clock enable.
ULTRA_HIGH_SPEED_MODE	Enable ultra high speed mode, use dll to generate clk.

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